LPDDR4/4x PHY IP for 22nm
DDR3L/ LPDDR4/ DDR4 PHY IP - 1866Mbps (Silicon Proven in UMC 28HPC+)
DDR4 You Can Use Now - RabotaKA.com
Register Automation for a DDR PHY Design
Synopsys Improves Memory Interface IP Integration - EEWeb
Taking a closer look at Rambus' HBM GEN2 PHY - The Next Platform
Memory Interface (DDR) PHY - CamverTech
DDR-PHY Interoperability Using DFI | Synopsys
Interface Macro｜Socionext Inc.
DDR4 Ping Pong PHY - YouTube
How to Verify JEDEC DRAM Memory Controller, PHY, or Memory Device? | ChipEstimate.com
Fast-Track AI Performance with the 24 Gb/s GDDR6 PHY - Embedded Computing Design
HBM2E PHY (High Bandwidth Memory) - Interface IP | Rambus
DDR PHY and Controller | Cadence
True Circuits, Inc.
Synopsys DDR4/3 PHY IP
DDR4 PHY - Rambus
DDR Memory Systems Compensate for Variations | Electronic Design
Atria Logic
DDR PHY Interface(DFI)
